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lpm quick reference guide december 1996
altera corporation iii about this quick reference guide december 1996 the lpm quick reference guide provides information on functions in the library of parameterized modules (lpm) and on custom parameterized functions created by altera . how to contact altera for additional information about altera products, consult the sources shown in table 1 . note: (1) you can also contact your local altera sales office or sales representative. see altera sales offices ?in this quick reference guide. table 1. how to contact altera information type access usa & canada all other locations literature altera express (800) 5-altera (408) 894-7850 altera literature services (888) 3-altera, note (1) (888) 3-altera; lit_req@altera.com, note (1) non-technical customer service telephone hotline (800) sos-epld (408) 894-7000 fax (408) 954-8186 (408) 954-8186 technical support telephone hotline (8:00 a.m. to 5 p.m. pacific time) (800) 800-epld (408) 894-7000, note (1) fax (408) 954-0348 (408) 954-0348, note (1) bulletin board service (408) 954-0104 (408) 954-0104 electronic mail sos@altera.com sos@altera.com ftp site ftp.altera.com ftp.altera.com compuserve go altera go altera general product information telephone (408) 894-7104 (408) 894-7104, note (1) world-wide web http://www.altera.com http://www.altera.com
iv altera corporation about this quic k ref erence guide t yp ographic conventions this lpm quick reference guide uses the typographic conventions shown in table 2 . table 2. lpm quick reference guide conventions visual cue meaning bold italics book titles are shown in bold italics, with initial capital letters. example: lpm quick reference guide ?ubheading title subheadings within a quick reference guide section and titles of max+plus ii help topics are shown in quotation marks. example: ?ltera sales offices courier font function names and port names are shown in lowercase courier. for example: lpm_and , data[] parameter names are shown in uppercase courier. for example: lpm_width , lpm_direction
altera corporation v contents december 1996 about this quick reference guide ............................................................................................................... iii how to contact altera .......................................................................................................................... iii typographic conventions .................................................................................................................... iv section 1: introduction ............................................................................................................................... 1 overview ............................................................................................................................... ................... 1 history of lpm ............................................................................................................................... ......... 1 lpm features ............................................................................................................................... ............ 2 lpm functions ............................................................................................................................... ......... 2 section 2: gate functions .......................................................................................................................... 3 lpm_and ............................................................................................................................... .................... 4 lpm_bustri ............................................................................................................................... ............. 5 lpm_clshift ............................................................................................................................... .......... 6 lpm_constant ............................................................................................................................... ........ 7 lpm_decode ............................................................................................................................... ............. 8 lpm_inv ............................................................................................................................... .................... 9 lpm_mux ............................................................................................................................... .................. 10 busmux ............................................................................................................................... .................... 11 mux ............................................................................................................................... ........................... 12 lpm_or ............................................................................................................................... .................... 13 lpm_xor ............................................................................................................................... .................. 14 section 3: arithmetic functions ............................................................................................................ 15 lpm_abs ............................................................................................................................... .................. 16 lpm_add_sub ............................................................................................................................... ........ 17 lpm_compare ............................................................................................................................... ........ 19 lpm_counter ............................................................................................................................... ........ 21 lpm_mult ............................................................................................................................... ............... 23
altera corporation vi contents section 4: storage functions ................................................................................................................. 25 lpm_ff ............................................................................................................................... .................... 26 lpm_latch ............................................................................................................................... ............. 28 lpm_ram_dq ............................................................................................................................... .......... 29 lpm_ram_io ............................................................................................................................... .......... 31 lpm_rom ............................................................................................................................... .................. 33 lpm_shiftreg ............................................................................................................................... ...... 34 section 5: custom parameterized functions ................................................................................... 37 csfifo ............................................................................................................................... .................... 38 CSDPRAM ............................................................................................................................... .................. 39 section 6: altera sales offices .............................................................................................................. 41 altera regional offices ........................................................................................................................ 41 altera international sales offices ....................................................................................................... 42
altera corporation 1 intr oduction december 1996 over view digital logic designers today must create designs consisting of tens-of- thousands of gates while meeting increased pressure to shorten time-to- market. at the same time, designers must maintain architecture- independence without sacrificing silicon efficiency. meeting these requirements with today? eda software tools is not easy. schematic-based design entry provides superior efficiency but implements architecture-dependent, low-level functions. high-level hardware description languages (hdls) offer architecture-independence, but offer reduced silicon efficiency and performance. because a standard set of functions supported by all eda and integrated circuit (ic) vendors was not previously available, bridging the gap between architecture-independence and efficiency was difficult. however, with the introduction of eda software tools that support the library of parameterized modules (lpm), designers can now create architecture-independent designs that have high silicon efficiency. histor y of lpm the lpm standard was proposed in 1990 to enable efficient mapping of digital designs to diverse architectures such as programmable logic devices (plds), gate arrays, and standard cells. the lpm was accepted as an electronic industries association (eia) interim standard in april 1993 as an adjunct standard to the electronic design interface format (edif), an industry-standard syntax that describes a structural netlist. edif can be used to transfer designs between the different software tools of eda vendors and from eda tools to ic tools. lpm functions describe the logical operation of the netlist. lpm functions used in a design can be directly passed to the ic vendor? design implementation software through an edif netlist file. before the arrival of the lpm standard, each edif netlist would typically contain architecture-specific logic functions, which made architecture-independent design impossible. lpm functions are compatible with any text or graphic design entry tool, and are supported by altera through max+plus ii and major eda tool vendors, including cadence, exemplar, mentor graphics, minc, summit design, synopsys, veribest, and viewlogic. altera has supported the standard since 1993, and many other silicon companies will support the lpm standard by the end of 1997.
2 altera corporation intr oduction lpm features the primary objective for the lpm is to enable architecture-independent design without sacrificing efficiency. the lpm meets the following key criteria: n architecture-independent design entry ?esigners can work with lpm functions during design entry and verification without specifying the target architecture. design entry and simulation tools remain architecture-independent, relying on the synthesis or fitting tools to efficiently map the design to various architectures. n efficient design mapping ?he lpm allows designers to create architecture-independent designs without sacrificing efficiency. the ic vendor is responsible for the mapping of lpm functions; thus, optimum solutions are guaranteed. n tool-independent design entry ?he lpm enables designers to migrate designs between eda tools while maintaining a high-level logic description of the functions. for example, designers can use one vendor? tool for logic synthesis and another vendor? tool for logic simulation. n specification of a complete design ?pm functions completely specify the digital logic for any design. designers can create new functions with lpm functions. lpm functions the lpm presently contains 25 functions. despite its small size, the lpm can duplicate the functionality of other design libraries that contain many more functions; each function contains parameters that allow it to expand in many dimensions. for example, the lpm_counter function allows the user to create counters with widths ranging from 1 to 256 bits. in addition to width, the user can specify the features and functionality of the counter. for example, parameters indicate whether the counter counts up or down, or loads synchronously or asynchronously. thus, the single lpm_counter function can replace over thirty 74-series counters.
altera corporation 3 gate functions december 1996 lpm_and ............................................................................................................................... ............................. 4 lpm_bustri ............................................................................................................................... ...................... 5 lpm_clshift ............................................................................................................................... ................... 6 lpm_constant ............................................................................................................................... ................. 7 lpm_decode ............................................................................................................................... ...................... 8 lpm_inv ............................................................................................................................... ............................. 9 lpm_mux ............................................................................................................................... ........................... 10 busmux ............................................................................................................................... ............................. 11 mux ............................................................................................................................... .................................... 12 lpm_or ............................................................................................................................... ............................. 13 lpm_xor ............................................................................................................................... ........................... 14
4 altera corporation gate functions lpm_and parameterized and gate ports parameters name type required description data[][] input yes data input to the and gate(s). this port consists of lpm_size buses, each lpm_width wide. result[] output yes each result[] bit is the and of all data[lpm_size?..0][] inputs. this port is lpm_width wide. name required value description lpm_size yes integer > 0 number of inputs to each and gate. lpm_width yes integer > 0 width of the result[] port. number of and gates. data[][] lpm_and result[] lpm_size= lpm_width=
altera corporation 5 gate functions lpm_bustri parameterized tri-state buffer the lpm_bustri function can be used to cr eate both unidir ectional and bidir ectional tri-state bus contr ollers. ports parameters name type required description data[] input yes data input to the tridata[] bus. this port is lpm_width wide. enabletr input no if high, enables tridata[] onto the result[] bus. required if result[] is present (default = 0). enabledt input yes if high, enables data[] onto the tridata[] bus. result[] output no this port is lpm_width wide. tridata[] bidirectional yes bidirectional bus signal. this port is lpm_width wide. name required value description lpm_width yes integer > 0 width of the data[] , result[] , and tridata[] ports. lpm_width= lpm_b ustri result[] data[] enab ledt tr idata[] enab letr
6 altera corporation gate functions lpm_clshift parameterized combinatorial logic shifter or barrel shifter the lpm_clshift function performs logical, r otational, or arithmetic combinatorial shifting. the dir ection and distance of the shifting ar e user - contr ollable. ports parameters name type required description data[] input yes data to be shifted. this port is lpm_width wide. distance[] input yes number of positions to shift data[] in the direction specified by the direction port. this port is lpm_widthdist wide. direction input no direction of shift. low = left (toward the most significant bit (msb)), high = right (toward the least significant bit (lsb)). default value is 0 (low) = left (toward the msb). result[] output yes shifted data. this port is lpm_width wide. underflow output no logical or arithmetic underflow. if "rotate" is specified as the lpm_shifttype parameter value and overflow and underflow are connected, the output of overflow and underflow will be undefined logic levels. overflow output no logical or arithmetic overflow. if "rotate" is specified as the lpm_shifttype parameter value and overflow and underflow are connected, the output of overflow and underflow will be undefined logic levels. name required value description lpm_shifttype no "logical" "rotate" "arithmetic" the sign bit is extended for "arithmetic" right shifts. for a "logical" right shift, 0s are always shifted into the msb or lsb. the default value is "logical" . lpm_width yes integer > 1 width of the data[] and result[] ports. lpm_widthdist yes integer > 0 width of the distance[] port. the distance[] port values normally range from 0, which is ?o shift,?to ( lpm_width ?1), which is the maximum meaningful shift. the typical value assigned to lpm_widthdist is ?he smallest integer not less than log 2 ( lpm_width )?or ceil(log 2 ( lpm_width )). any distance[] port value greater than ( lpm_width ?1) results in an undefined logic level. data[] distance[] direction result[] underflo w o v erflo w lpm_clshift lpm_shifttype= lpm_width= lpm_widthdist=ceil(log2(lpm_width))
altera corporation 7 gate functions lpm_constant parameterized constant generator the lpm_constant function applies a constant to a bus. this function is useful for comparisons and arithmetic functions that operate on a constant value. ports parameters name type required description result[] output yes value specified by the argument to lpm_cvalue . this port is lpm_width wide. the lpm_cvalue parameter is truncated or zero-padded to lpm_width bits. name required value description lpm_cvalue yes integer 3 0 constant value to be driven out on the result[] port. if lpm_cvalue cannot be represented in lpm_width bits, the result[] port drives the value lpm_cvalue mod 2 lpm_width . lpm_width yes integer > 0 width of the result[] port. lpm_const ant (cv alue) result[] lpm_cv alue= lpm_width=
8 altera corporation gate functions lpm_decode parameterized decoder ports parameters name type required description clock input no clock for pipelined usage. the clock port provides pipelined operation for lpm_decode . for lpm_pipeline values other than 0 (default value), the clock port must be connected. aclr input no asynchronous clear for pipelined usage. the pipeline initializes to undefined. the aclr port can be used at any time to reset the pipeline to all 0s, asynchronously to the clock. data[] input yes data input. treated as an unsigned binary-encoded number. this port is lpm_width wide. enable input no enable. all outputs are low when this port is inactive. if absent, the default value is active (high). eq[] output yes output of the decoder. this port is lpm_decodes wide. if data[] 3 lpm_decodes , all eq[] outputs are 0. name required value description lpm_decodes yes 2 lpm_width 3 integer > 0 number of explicit decoder outputs. the default value is 2 lpm_width . lpm_pipeline no integer 3 0 specifies the number of clock cycles of latency associated with the eq[] output. a value of zero (0) indicates that no latency exists, and that a purely combinatorial function will be instantiated. the default value is 0 (non-pipelined). lpm_width yes integer > 0 width of the input value to be decoded. lpm_decode lpm_decodes=2^lpm_width lpm_pipeline= lpm_width= eq[] cloc k aclr data[] enab le
altera corporation 9 gate functions lpm_inv parameterized inverter ports parameters name type required description data[] input yes data input to the lpm_inv function. this port is lpm_width wide. result[] output yes inverted result. this port is lpm_width wide. name required value description lpm_width yes integer > 0 width of the data[] and result[] ports. data[] result[] lpm_inv lpm_width=
10 altera corporation gate functions lpm_mux parameterized multiplexer ports parameters name type required description aclr input no asynchronous clear for pipelined usage. the pipeline initializes to undefined. the aclr port can be used at any time to reset the pipeline to all 0s, asynchronously to the clock. data[][] input yes data input. this port consists of lpm_size buses, each lpm_width wide. clock input yes clock for pipelined usage. the clock port provides pipelined operation for lpm_mux . for lpm_pipeline values other than 0 (default value), the clock port must be connected. sel[] input yes selects one of the input buses. this port is lpm_widths wide. result[] output yes selected input port. this port is lpm_width wide. name required value description lpm_pipeline no integer 3 0 specifies the number of clock cycles of latency associated with the result[] output. a value of zero (0) indicates that no latency exists, and that a purely combinatorial function will be instantiated. the default value is 0 (non-pipelined). lpm_size yes 2 lpm_widths 3 integer > 1 number of inputs to each multiplexer. number of input buses. lpm_width yes integer > 0 width of the data[][] and result[] ports. lpm_widths yes integer > 0 width of the sel[] port. the default value is ceil(log 2 ( lpm_size )). data[][] result[] sel[] lpm_mux cloc k aclr lpm_pipeline= lpm_size= lpm_width= lpm_widths=ceil(log2(lpm_size))
altera corporation 11 gate functions busmux parameterized multiplexer the busmux function is an altera-pr ovided function derived fr om lpm_mux and is intended to simplify the use of lpm_mux in graphic design files ( .gdf ). the busmux function is an instance of lpm_mux with lpm_size set to 2. ports parameters name type required description dataa[] input yes data input to the busmux . this port is width wide. datab[] input yes data input to the busmux . this port is width wide. sel input yes selects one of the ports. result[] output yes the selected input port. this port is width wide. name required value description width yes integer > 0 width of the dataa[] , datab[] , and result[] ports. 0 1 dataa[] datab[] result[] sel width= b usmux
12 altera corporation gate functions mux parameterized multiplexer the mux function is an altera-pr ovided function derived fr om lpm_mux and is intended to simplify the use of lpm_mux in gdfs. the mux function is an instance of lpm_mux with lpm_width set to 1. ports parameters name type required description data[] input yes data input to the mux . this port is width wide. sel[] input yes selects one of the ports. this port is widths wide. result output yes the selected input port. this port is 1 bit wide. name required value description width yes integer > 0 width of the data[] port. widths yes integer > 0 width of the sel[] port. the default value is ceil(log 2 ( width )). data[] result sel[] width= widths=ceil(log2(width)) mux
altera corporation 13 gate functions lpm_or parameterized or gate ports parameters name type required description data[][] input yes data input to the or gate(s). this port consists of lpm_size buses, each lpm_width wide. result[] output yes result of or operators. this port is lpm_width wide. name required value description lpm_width yes integer > 0 width of the data[][] and result[] ports. number of or gates. lpm_size yes integer > 0 number of inputs to each or gate. number of input buses. data[][] result[] lpm_or lpm_width= lpm_size=
14 altera corporation gate functions lpm_xor parameterized xor gate ports parameters name type required description data[][] input yes data input to the xor gate(s). this port consists of lpm_size buses, each lpm_width wide. result[] output yes each result[] bit is the xor of lpm_size bits. this port is lpm_width wide. name required value description lpm_size yes integer > 0 number of inputs to each xor gate. number of input buses. lpm_width yes integer > 0 width of the data[][] and result[] ports. number of xor gates. data[][] result[] lpm_xor lpm_size= lpm_width=1
altera corporation 15 arithmetic functions december 1996 lpm_abs ............................................................................................................................... .......................... 16 lpm_add_sub ............................................................................................................................... ................ 17 lpm_compare ............................................................................................................................... ................ 19 lpm_counter ............................................................................................................................... ................. 21 lpm_mult ............................................................................................................................... ........................ 23
16 altera corporation arithmetic functions lpm_abs parameterized absolute value ports parameters name type required description data[] input yes signed number. this port is lpm_width wide. result[] output yes absolute value of data[] . this port is lpm_width wide . overflow output no high if data[] = ? ( lpm_width ?1) . two? complement allows one more negative number than positive. the overflow port detects that singular instance and goes high to indicate that no positive equivalent exists. name required value description lpm_width yes integer 3 0 width of the data[] and result[] ports. data[] result[] o v erflo w lpm_abs lpm_width=
altera corporation 17 arithmetic functions lpm_add_sub parameterized adder/subtractor ports name type required description add_sub input no if the input is high, the operation = dataa[] + datab[] . if the input is low, the operation = dataa[] datab[] . this port cannot be used if the lpm_direction parameter is used. if both the add_sub port and the lpm_direction parameter are omitted, the operation defaults to "add" . cin input no carry-in to the low-order bit. if the operation is "add" , low = 0 and high = +1. if the operation is "sub" , low = ? and high = 0. if omitted, the default is 0 (i.e., no affect on "add" or "sub" operations). dataa[] input yes augend/minuend. this port is lpm_width wide. clock input no clock for pipelined usage. the clock port provides pipelined operation of lpm_add_sub . for lpm_pipeline values other than 0 (default value), the clock port must be connected. datab[] input yes addend/subtrahend. this port is lpm_width wide. aclr input no asynchronous clear for pipelined usage. the pipeline initializes to undefined. the aclr port can be used at any time to reset the pipeline to all 0s, asynchronously to clock . result[] output yes dataa[] + or ? datab[] + or ? cin . this port is lpm_width wide. overflow output no result exceeds available precision. if overflow is used, cout cannot be used. the overflow signal has a physical interpretation as the xor of the carry into the msb with the carry out of the msb. the overflow signal is only meaningful when the lpm_representation parameter is set to "signed" . note (1) cout output no carry-out (borrow-in) of the msb. if overflow is used, cout cannot be used. the cout signal has a physical interpretation as the carry-out (borrow-in) of the msb and is most meaningful for detecting overflow in "unsigned" operations. note (2) cin result[] dataa[] datab[] cout lpm_add_sub lpm_direction= lpm_pipeline= lpm_represent a tion= lpm_width= one_input_is_const ant= add_sub o v erflo w cloc k aclr
18 altera corporation arithmetic functions parameters notes: (1) the following table describes the overflow port during "add" and "sub" operations. (2) the following table describes the cout port during "add" and "sub" operations. name required value description lpm_direction no "add" "sub" "default" the add_sub port cannot be used if the lpm_direction parameter is has a value other than "default" . the default value is "default" . lpm_pipeline no integer 3 0 specifies the number of clock cycles of latency associated with the result[] output. a value of zero ( 0 ) indicates that no latency exists, and that a purely combinatorial function will be instantiated. the default value is 0 (non-pipelined). lpm_representation no "signed" "unsigned" type of addition performed. the default value is "signed" . lpm_width yes integer > 0 width of the dataa[] , datab[] , and result[] ports. one_input_is_constant no "yes" "no" provides greater optimization if an input is constant. the default value is "no" . value add operation sub operation "unsigned" not meaningful. not meaningful. "signed" ( dataa + datab + cin ) > 2 ( lpm_width ?1) ?1 or ( dataa + datab + cin ) > 2 ( lpm_width ?1) ( dataa ? datab ? cin ) > 2 ( lpm_width ?1) ?1 or ( dataa ? datab ? cin ) > 2 ( lpm_width ?1) value add operation sub operation "unsigned" dataa + datab + cin > 2 ( lpm_width ?1) ?1 normal subtract. however, if cout = 0, then ( dataa ? datab ? cin ) < 0. "signed" normal result of adding two negative numbers, or possible overflow. normal result when subtracting a positive number from a negative number, or possible overflow.
altera corporation 19 arithmetic functions lpm_compare parameterized comparator ports name type required description dataa[] input yes the datab[] signal is compared to this value. this port is lpm_width wide. datab[] input yes value to be compared to dataa[] . this port is lpm_width wide. clock input no clock for pipelined usage. the clock port provides pipelined operation for lpm_compare . for lpm_pipeline values other than 0 (default value), the clock port must be connected. aclr input no asynchronous clear for pipelined usage. the pipeline initializes to undefined. the aclr port can be used at any time to reset the pipeline to all 0s, asynchronously to clock . alb output no high (1) if dataa[] < datab[] . one of the alb , aeb , agb , ageb , aleb , or aneb outputs must be present. aeb output no high (1) if dataa[] = datab[] . one of the alb , aeb , agb , ageb , aleb , or aneb outputs must be present. agb output no high (1) if dataa[] > datab[] . one of the alb , aeb , agb , ageb , aleb , or aneb outputs must be present. ageb output no high (1) if dataa[] 3 datab[] . one of the alb , aeb , agb , ageb , aleb , or aneb outputs must be present. aneb output no high (1) if dataa[] 1 datab[] . one of the alb , aeb , agb , ageb , aleb , or aneb outputs must be present. aleb output no high (1) if dataa[] datab[] . one of the alb , aeb , agb , ageb , aleb , or aneb outputs must be present. dataa[] datab[] cloc k aclr lpm_comp are alb aeb agb ageb aneb aleb chain_size= lpm_pipeline= lpm_represent a tion= lpm_width= one_input_is_const ant=
20 altera corporation arithmetic functions parameters name required value description chain_size no integer > 0 maximum allowable length of carry chains or cascade chains in flex 10k and flex 8000 devices. the default value is 8. in max+plus ii, this value overrides the value of the max. auto length option for the carry chain or cascade chain logic option(s) in the global project logic synthesis style, which is specified with the global project logic synthesis dialog box (assign menu). for other device families, varying the chain_size parameter will provide different speed/size combinations?etting smaller values for chain_size generally results in faster and larger comparators and vice versa. for more information, contact altera applications. lpm_pipeline no integer 3 0 specifies the number of clock cycles of latency associated with the alb , aeb , agb , ageb , aneb , and aleb outputs. a value of zero (0) indicates that no latency exists, and that a purely combinatorial function will be instantiated. default value is 0 (non-pipelined). lpm_representation no "signed" "unsigned" type of comparison performed. the default value is "unsigned" . lpm_width yes integer > 0 width of the dataa[] and datab[] ports. one_input_is_constant no "yes" "no" provides greater optimization if an input is constant. the default value is "no" .
altera corporation 21 arithmetic functions lpm_counter parameterized counter the lpm_counter function is a full- featur ed counter with loading, up/down contr ol, clock, and count enabling and clearing. ports (part 1 of 2) name type required description sset input no synchronous set input. sets the counter on the next active clock edge. default = 0. sets q[] outputs to all 1s, or to the value specified by lpm_svalue . if both sset and sclr are used and both are asserted, sclr is dominant. for outputs such as q[] and eq[] , sset affects the output before polarity is applied. sload input no synchronous load input. loads the counter with data on the next active clock edge. default = 0. if sload is used, data[] must be connected. updown input no controls the direction of the count. high (1) = count up. low (0) = count down. default = up (1). if the lpm_direction parameter is used, the updown port cannot be connected. if lpm_direction is not used, the updown port is optional. cnt_en input no count enable input. disables count when low (0) without affecting sload , sset , or sclr . default = 1. data[] input no parallel data input to the counter. this port is lpm_width wide. uses aload and/or sload . clock input yes positive-edge-triggered clock. clk_en input no clock enable input. enables all synchronous activities. default = 1. sconst input no this port is provided only for backwards-compatibility in max+plus ii pre-version 6.0 designs. altera does not recommend using this port for new designs. sclr input no synchronous clear input. clears the counter on the next active clock edge. default = 0. if both sset and sclr are used and both are asserted, sclr is dominant. for outputs such as q[] and eq[] , sclr affects the output before polarity is applied. sset sload updo wn cnt_en data[] cloc k clk_en sconst sclr lpm_counter lpm_sv alue= lpm_a v alue= lpm_modulus= lpm_direction= lpm_width= q[] eq[] aset aclr aload aconst
22 altera corporation arithmetic functions parameters name type required description aset input no asynchronous set input. default = 0. sets q[] outputs to all 1s, or to the value specified by lpm_avalue . if both aset and aclr are used and both are asserted, aclr is dominant. for outputs such as q[] and eq[] , aset affects the output before polarity is applied. aclr input no asynchronous clear input. default = 0. if both aset and aclr are used and both are asserted, aclr is dominant. for outputs such as q[] and eq[] , aclr affects the output before polarity is applied. aload input no asynchronous load input. asynchronously loads the counter with the value on the data input. default = 0. if aload is used, data[] must be used. aconst input no this port is provided only for backwards-compatibility in max+plus ii pre-version 6.0 designs. altera does not recommend using this port in new designs. eq[] output no counter decode output. active high when the counter reaches the specified count value. either the q[] port or eq[] port must be connected. up to c eq ports can be used ( c 15). only the 16 lowest count values are decoded. when the count value is c , the eq c output is set high (1). for example, when the count is 0, eq 0 = 1, when the count is 1, eq 1 = 1, and when the count is 15, eq 15 = 1. decoded outputs for count values of 16 or greater require external decoding. the eq c outputs are asynchronous. q[] output no data output from the counter. this port is lpm_width wide. either q[] or at least one of the eq[] ports must be connected. name required value description lpm_svalue no integer 3 0 constant value that is loaded on the rising edge of clock when sset is high. must be used if sset is used. lpm_avalue no integer 3 0 constant value that is loaded when aset is high. this parameter must be used if aset is used. if the value specified is larger than the < modulus >, the behavior of the counter is an undefined logic level. the < modulus > is lpm_modulus , if present, or 2 lpm_width . lpm_modulus no integer > 1 the maximum count, plus one. number of unique states in the counter? cycle. if the load value is larger than the lpm_modulus parameter, the behavior of the counter is not specified. the default value is 2 lpm_width . lpm_direction no "up" "down" "default" if the lpm_direction parameter is used, the updown port cannot be connected. when the updown port is not connected, the count direction is " up ". in all other cases, the default value is "default" . lpm_width yes integer > 0 width of the input and output ports. if no output ports are specified, the value is the number of bits in the count. ports (part 2 of 2)
altera corporation 23 arithmetic functions lpm_mult parameterized multiplier the lpm_mult function allows two signed or unsigned numbers to be multiplied. in addition, the r esult of the multiplication can be added to a thir d number . ports name type required description clock input no clock for pipelined usage. the clock port provides pipelined operation for lpm_mult . for lpm_pipeline values other than 0 (default value), the clock port must be connected. dataa[] input yes multiplicand. this port is lpm_widtha wide. sum[] input no partial sum. this port is lpm_widths wide. datab[] input yes multiplier. this port is lpm_widthb wide. aclr input no asynchronous clear for pipelined usage. the pipeline initializes to undefined. the aclr port can be used at any time to reset the pipeline to all 0s, asynchronously to clock . result[] output yes this port is lpm_widthp wide. if lpm_widthp < max ( lpm_widtha + lpm_widthb, lpm_widths ) or ( lpm_widths) , only the lpm_widthp msbs are present. lpm_mul t result[] dataa[] datab[] input_a_is_const ant= input_b_is_const ant= lpm_pipeline= lpm_represent a tion= lpm_widtha= lpm_widthb= lpm_widthp=(lpm_widtha+lpm_widthb) lpm_widths=lpm_widtha cloc k sum[] aclr
24 altera corporation arithmetic functions parameters note: (1) the latency parameter is provided only for backwards-compatibility with max+plus ii pre-version 7.0 designs. for all new designs, you should use the lpm_pipeline parameter instead. name required value description input_a_is_constant no "yes" "no" if dataa[] is connected to a constant value, setting the value of input_a_is_constant to "yes" optimizes the multiplier for resource usage and speed. the default value is "no" . input_b_is_constant no "yes" "no" if datab[] is connected to a constant value, setting the value of input_b_is_constant to "yes" optimizes the multiplier for resource usage and speed. the default value is "no" . lpm_pipeline no integer 3 0 specifies the number of clock cycles of latency associated with the result[] output. the default value of zero ( 0 ) indicates that no latency exists, and that a purely combinatorial function will be instantiated. the default value is 0 (non-pipelined). lpm_representation no "signed" "unsigned" type of multiplication performed. the default value is "unsigned" . lpm_widtha yes integer > 0 width of the dataa[] port. lpm_widthb yes integer > 0 width of the datab[] port. lpm_widthp yes integer > 0 width of the result[] port. the default is lpm_widtha+lpm_widthb . lpm_widths no integer > 0 width of the sum[] port. if the sum[] port is not used, lpm_widths must be set to a value between 1 and lpm_widthp , inclusive. the default value is lpm_widtha . latency , note (1) no integer 3 0 same as lpm_pipeline .
altera corporation 25 stora g e functions december 1996 lpm_ff ............................................................................................................................... ............................. 26 lpm_latch ............................................................................................................................... ...................... 28 lpm_ram_dq ............................................................................................................................... .................... 29 lpm_ram_io ............................................................................................................................... .................... 31 lpm_rom ............................................................................................................................... ........................... 33 lpm_shiftreg ............................................................................................................................... ............... 34
26 altera corporation stora g e functions lpm_ff parameterized d or t flipflop ports name type required description aload input no asynchronous load input. asynchronously loads the flipflop with the value on the data[] input. default = 0. if aload is used, data[] must be used. sset input no synchronous set input. sets the q[] outputs to the value specified by lpm_svalue , if that value is present, or sets the q[] outputs to all 1s. if both sset and sclr are used and both are asserted, sclr is dominant. the sset input affects the output q[] values before polarity is applied to the ports. sload input no synchronous load input. loads the flipflop with the value on the data[] input on the next active clock edge. default = 0. if sload is used, data[] must be used. for load operation, sload must be high (1) and enable must be high (1) or unconnected. data[] input no t flipflop: toggle enable; d flipflop: data input. this port is lpm_width wide. if the data[] port is not used, at least one of the aset , aclr , sset , or sclr ports must be used. clock input yes positive-edge-triggered clock. enable input no clock enable input. default = 1. sclr input no synchronous clear input. if both sset and sclr are used and both are asserted, sclr is dominant. the sclr input affects the output q[] values before polarity is applied to the ports. aset input no asynchronous set input. sets q[] outputs to the value specified by lpm_avalue , if that value is present, or sets the q[] outputs to all 1s. aclr input no asynchronous clear input. if both aset and aclr are used and both are asserted, aclr is dominant. the aclr input affects the output q[] values before polarity is applied to the ports. q[] output yes data output from d flipflops. this port is lpm_width wide. aload sset sload data[] cloc k enab le sclr lpm_ff lpm_a v alue= lpm_fftype= lpm_sv alue= lpm_width= q[] aclr aset
altera corporation 27 stora g e functions parameters name required value description lpm_avalue yes integer 3 0 constant value that is loaded when aset is high. the default value is all 1s. lpm_fftype no "dff" "tff" type of flipflop. the default value is "dff" . lpm_svalue no integer 3 0 constant value that is loaded on the rising edge of clock when sset is high. the default value is all 1s. lpm_width yes integer > 0 width of the data[] and q[] ports.
28 altera corporation stora g e functions lpm_latch parameterized latch ports parameters name type required description aset input no asynchronous set input. default = 0. sets q[] outputs to the value specified by lpm_avalue , if that value is present. if no lpm_avalue is specified, aset will set the count to all 1s. if both aset and aclr are used and both are asserted, aclr is dominant. the aset and aclr inputs affect the output q[] values before polarity is applied to the ports. data[] input no data input to the d-type latch. this port is lpm_width wide. if the data[] port is not used, either aset or aclr must be used. gate input yes latch enable input. high = flow-through, low = latch. aconst input no this port is provided only for backwards-compatibility in max+plus ii pre-version 6.0 designs. altera does not recommend using this port in new designs. aclr input no asynchronous clear input. default = 0. sets the latch to all 0s. if both aset and aclr are used and both are asserted, aclr is dominant. the aset and aclr inputs affect the output q[] values before the polarity is applied to the ports. q[] output yes data output from the latches. this port is lpm_width wide. name required value description lpm_width yes integer > 0 width of the data[] and q[] ports. lpm_avalue no integer 3 0 constant value that is loaded when aset is high. the default value of lpm_avalue is all 1s. lpm_la tch aset data[] gate aconst aclr lpm_width= lpm_a v alue= q[]
altera corporation 29 stora g e functions lpm_ram_dq parameterized random access memory with separate input and output ports the lpm_ram_dq function can be used as either synchr onous or asynchr onous random access memory . the lpm_ram_dq function has separate input and output data buses. ports name type required description data[] input yes data input to memory. this port is lpm_width wide. address[] input yes address input to the memory. this port is lpm_widthad wide. inclock input no synchronizes memory loading. if the inclock port is used, the we port acts as an enable for write operations synchronized to the rising edge of the inclock input. if the inclock port is not used, the we port acts as an enable for asynchronous write operations. outclock input no synchronizes q[] outputs from memory. the addressed memory content ? q[] response is synchronous when the outclock port is connected, and asynchronous when it is not connected. we input yes write enable input. when high, enables write operation to the memory. required if inclock is not present. if only we is used, the data on the address[] port should not change while we is high. if the data on the address[] port changes while we is high, all memory locations that are addressed are overwritten with data[] . q[] output yes data output from the memory. this port is lpm_width wide. lpm_ram_dq data[] address[] incloc k outcloc k w e lpm_address_contr ol= lpm_file= lpm_ind a t a= lpm_numw ords= lpm_outd a t a="unregistered" lpm_width= lpm_widthad= q[]
30 altera corporation stora g e functions parameters name required value description lpm_address_control no "registered" "unregistered" controls whether the address[] and we ports are registered. the default value is "registered" . lpm_file no "< filename >" name of the memory initialization file ( .mif ) or hexadecimal file ( .hex ) containing ram initialization data ("< filename >"). if omitted, contents default to all 0s. lpm_indata no "registered" "unregistered" controls whether the data[] port is registered. the default value is "registered" . lpm_numwords no integer > 0 number of words stored in memory. in general, this value should be (but is not required to be): 2 lpm_widthad ?1 < lpm_numwords 2 lpm_widthad . the default value is 2 lpm_widthad . lpm_outdata no "registered" "unregistered" controls whether the q[] and internal eq ports are registered. the default value is "registered" . lpm_width yes integer > 0 width of the data[] and q[] ports. lpm_widthad yes integer > 0 width of the address[] port. lpm_widthad should be (but is not required to be): log 2 ( lpm_numwords ). if lpm_widthad is too small, some memory locations will not be addressable. if lpm_widthad is too large, the addresses that are too high will return undefined logic levels.
altera corporation 31 stora g e functions lpm_ram_io parameterized random access memory with a single i/o port the lpm_ram_io function can be used as either synchr onous or asynchr onous random access memory . the lpm_ram_io function has a bidir ectional bus. ports name type required description address[] input yes address input to the memory. this port is lpm_widthad wide. if memenab is used, it should be inactive when address[] is changing. inclock input no synchronizes memory loading. if the inclock port is used, the we port acts as an enable for write operations synchronized to the rising edge of the inclock input. if the inclock port is not used, the we port acts as an enable for asynchronous write operations. outclock input no synchronizes dio[] from memory. the addressed memory content ? q[] response is synchronous when the outclock port is connected, and asynchronous when it is not connected. we input yes write enable input. either we or outenab should be used. when high, enables write operations to the memory. if no clock ports are used, the data on the address[] port should not change when we is high (1). required if clock is not present. if we is absent, the default value is enabled. outenab input no output enable input. high (1): dio[] from memory address[] . low (0): memory address[] from dio[] . either memenab or outenab must be present. memenab input no memory output tri-state enable. either memenab or outenab must be connected. if memenab is present, it should be inactive when address[] is changing. dio[] bidirectional yes data port for the memory. this port is lpm_width wide. lpm_ram_io address[] incloc k outcloc k w e outenab memenab lpm_address_contr ol= lpm_file= lpm_ind a t a= lpm_numw ords= lpm_outd a t a="unregistered" lpm_width= lpm_widthad= dio[]
32 altera corporation stora g e functions parameters name required value description lpm_address_control no "registered" "unregistered" controls whether the address[] , memenab , and we ports are registered. the default value is "registered" . lpm_file no "< filename >" name of the mif or hex file containing rom initialization data ("< filename >"). if omitted, contents default to all 0s. lpm_indata no "registered" "unregistered" controls whether the internal data port is registered. the default value is "registered" . lpm_numwords no integer > 0 number of words stored in memory. in general, this value should be (but is not required to be): 2 lpm_widthad ? < lpm_numwords 2 lpm_widthad . the default value is 2 lpm_widthad . lpm_outdata no "registered" "unregistered" controls whether the dio[] port is registered. the default value is "registered" . lpm_width yes integer > 0 width of dio[] and internal data and q ports. lpm_widthad yes integer > 0 width of the address[] port. lpm_widthad should be (but is not required to be) equal to log 2 ( lpm_numwords ). if lpm_widthad is too small, some memory locations will not be addressable. if it is too large, the addresses that are too high will return undefined logic levels.
altera corporation 33 stora g e functions lpm_rom parameterized read-only memory the lpm_rom function can be used as either synchr onous or asynchr onous r ead-only memory . ports parameters name type required description address[] input yes address input to the memory. this port is lpm_widthad wide. inclock input no clock for input registers. the address[] port is synchronous (registered) when the inclock port is connected, and is asynchronous (unregistered) when the inclock port is not connected. outclock input no clock for output registers. the addressed memory content ? q[] response is synchronous when the outclock port is connected, and is asynchronous when it is not connected. memenab input no memory enable input. high = data output on q[] , low = high-impedance outputs. q[] output yes memory output. this port is lpm_width wide. name required value description lpm_address_control no "registered" "unregistered" controls whether the address[] port is registered. the default value is "registered" . lpm_file yes "< filename >" name of the mif or hex file containing rom initialization data ("< filename >"). lpm_numwords no integer > 0 in general, this value should be (but is not required to be) 2 lpm_widthad ? < lpm_numwords 2 lpm_widthad . the default value is 2 lpm_widthad . lpm_outdata no "registered" "unregistered" controls whether the q[] port is registered. the default value is "registered" . lpm_width yes integer > 0 width of the q[] port. lpm_widthad yes integer > 0 width of the address[] port. lpm_widthad should be (but is not required to be) equal to log 2 ( lpm_numwords ). if lpm_widthad is too small, some memory locations will not be addressable. if it is too large, the addresses that are too high will return undefined logic levels. lpm_r om address[] incloc k outcloc k memenab lpm_address_contr ol= lpm_file= lpm_numw ords= lpm_outd a t a="unregistered" lpm_width= lpm_widthad= q[]
34 altera corporation stora g e functions lpm_shiftreg parameterized shift register ports name type required description sclr input no synchronous clear input. if both sset and sclr are used and both are asserted, sclr is dominant. the sclr input affects the output q[] values before polarity is applied to the ports. sset input no synchronous set input. sets q[] outputs to the value specified by lpm_svalue , if that value is present, or sets the q[] outputs to all 1s. if both sset and sclr are used and both are asserted, sclr is dominant. the sset input affects the output q[] values before polarity is applied to the ports. shiftin input no serial shift data input. at least one of the data[] , aset , aclr , sset , sclr , and/or shiftin ports must be used. load input no synchronous parallel load. high (1): load operation; low (0): shift operation. default is low (0) shift operation. for parallel load operation, load must be high (1) and enable must be high or unconnected. data[] input no data input to the shift register. this port is lpm_width wide. at least one of the data[] , aset , aclr , sset , sclr and/or shiftin ports must be used. clock input yes positive-edge-triggered clock. default = 1. enable input no clock enable input. the shift options also use the enable input for the clock enable. for serial operation, both shiftin and enable must be high. aclr input no asynchronous clear input. if both aset and aclr are used and both are asserted, aclr is dominant. the aclr input affects the output q[] values before polarity is applied to the ports. aset input no asynchronous set input. sets q[] outputs to the value specified by lpm_avalue , if that value is present, or sets the q[] outputs to all 1s. if both aset and aclr are used and both are asserted, aclr is dominant. the aset input affects the output q[] values before polarity is applied to the ports. shiftout output no serial shift data output. this port is lpm_width wide. either q[] or shiftout or both must be used. q[] output no data output from the shift register. this port is lpm_width wide. either q[] or shiftout or both must be used. sclr sset shiftin load data[] cloc k enab le lpm_shiftreg lpm_a v alue= lpm_direction= lpm_sv alue= lpm_width= q[] aclr aset shiftout
altera corporation 35 stora g e functions parameters name required value description lpm_avalue no integer > 0 constant value that is loaded when aset is high. lpm_direction no "left" "right" direction of the shift register. the default value is "left" . lpm_svalue no integer 3 0 constant value that is loaded on the rising edge of clock when sset is high. the default value is all 1s. lpm_width yes integer > 0 width of the data[] and q[] ports.
notes:
altera corporation 37 custom p arameteriz ed functions december 1996 csfifo ............................................................................................................................... ............................. 38 CSDPRAM ............................................................................................................................... ........................... 39
38 altera corporation custom p arameteriz ed functions cs fo cycle-shared fifo the csfifo function is a custom function that pr ovides a cycle-shar ed fifo with both dynamic and static user thr eshold level contr ols. it also of fers empty and full ag outputs. ports parameters name type required description data[] input yes data input to the csfifo . this port is lpm_width wide. wreq input yes write request. rreq input yes read request. clock input yes positive-edge-triggered clock. clockx2 input yes positive-edge-triggered clock. clr input no resets csfifo to empty. threshlevel[] input no level (number of words) that the threshold output signal asserts. q[] output yes data output from csfifo . this port is lpm_width wide. threshold output no indicates that csfifo contains greater than the threshlevel[] number of words. empty output no indicates that csfifo is empty. full output no indicates that csfifo is full. name required value description lpm_numwords no integer > 0 number of words stored in memory. in general, this value should be (but is not required to be): 2 lpm_width ?1 < lpm_numwords 2 lpm_widthad . the default value is 2 lpm_width . lpm_width yes integer > 0 width of the data[] and q[] ports. the default value is 8. csfifo data[] wreq rreq cloc k cloc kx2 clr threshle v el[] lpm_numw ords= lpm_width=8 q[] threshold empty full
altera corporation 39 custom p aramteriz ed functions CSDPRAM parameterized cycle-shared dual-port ram the CSDPRAM function is a custom function that has two addr ess and two data ports that ar e cycle-shar ed. this function also pr ovides a busy ag to indicate that the addr ess on both ports is pointing to the same location and that a port will have priority . ports parameters name type required description dataa[] input yes data input to the memory. this port is lpm_width wide. datab[] input yes data input to the memory. this port is lpm_width wide. addressa[] input yes address input to the memory. this port is lpm_widthad wide. addressb[] input yes address input to the memory. this port is lpm_widthad wide. wea input yes write enable input. web input yes write enable input. clock input yes positive-edge-triggered clock. clockx2 input yes positive-edge-triggered clock. qa[] output yes data output from the memory. this port is lpm_width wide. qb[] output yes data output from the memory. this port is lpm_width wide. busy output no indicates that addressa[] = addressb[] and that dataa[] is writing data. name required value description lpm_width yes integer > 0 width of the dataa[] , datab[] , qa[] , and qb[] ports. lpm_widthad yes integer > 0 width of the addressa[] and addressb[] ports. lpm_widthad should be (but is not required to be) equal to log 2 ( lpm_numwords ). if lpm_widthad is too small, some memory locations will not be addressable. if it is too large, the addresses that are too high will return undefined logic levels. lpm_numwords no integer > 0 number of words stored in memory. in general, this value should be (but is not required to be): 2 lpm_widthad ?1 < lpm_numwords 2 lpm_widthad . the default value is 2 lpm_widthad . CSDPRAM dataa[] datab[] addressa[] addressb[] w ea w eb cloc k cloc kx2 lpm_width= lpm_widthad= lpm_numw ords= qa[] qb[] b usy
notes:
altera corporation 41 altera sales of ces december 1996 altera regional of ces north ern california (corporate headquarters) altera corporation 2610 orchard parkway san jose, ca 95134-2020 tel: (408) 894-7000 fax: (408) 433-3943 (408) 894-7755 altera corporation 2290 n. first street, suite 212 san jose, ca 95131 tel: (408) 894-7900 fax: (408) 894-7979 southern california altera corporation 15375 barranca parkway, suite b-201 irvine, ca 92618 tel: (714) 450-0262 fax: (714) 450-0263 altera corporation olympic plaza executive center 11500 west olympic boulevard, suite 400 los angeles, ca 90064 tel: (310) 312-4507 fax: (310) 312-4508 altera corporation 5355 mira sorrento place, suite 100 san diego, ca 92121 tel: (619) 597-7518 fax: (619) 597-7418 arizona altera corporation 2390 e.camelback road, suite 300 phoenix, arizona 85016 tel: (602) 553-1090 fax: (602) 553-1198 colorado altera corporation denver technology center 7900 east union avenue, #1100 denver, co 80237 tel: (303) 694-5352 fax: (303) 694-5351 altera corporation 14142 denver west parkway, #200 golden, co 80401 tel: (303) 216-0167 fax: (303) 277-0429 georgia altera corporation 3675 crestwood parkway, suite 400 duluth, ga 30136 tel: (770) 935-6070 fax: (770) 935-6073 illinois altera corporation 475 n. martingale road, suite 420 schaumburg, il 60173 tel: (847) 240-0313 fax: (847) 240-0266 mar yland alter a cor por ation 9891 brok en land p ar kw a y , suite 300 columbia, md 21046 tel: (410) 312-5708 f ax: (410) 309-0720 massac husetts altera corporation 238 littleton road, suite 207 westford, ma 01886 tel: (508) 392-1100 fax: (508) 392-1157 minnesota alter a cor por ation 2850 metro dr iv e , suite 250 bloomington, mn 55425 tel: (612) 851-7861 f ax: (612) 858-7258 ne w jer se y altera corporation 575 state highway 28 raritan, nj 08869 tel: (908) 526-9400 fax: (908) 526-5471 nor th car olina altera corporation 5511 capital center drive, suite 110 raleigh, nc 27606 tel: (919) 852-1004 fax: (919) 852-0809 ohio altera corporation 7784 reynolds road mentor, oh 44060 tel: (216) 946-8211 fax: (216) 946-9411
42 altera corporation altera sales of ces altera international sales of ces united states (corporate headquarters) altera corporation 2610 orchard parkway san jose, ca 95134-2020 usa tel: (408) 894-7000 fax: (408) 433-3943 (408) 894-7755 united kingdom (eur opean headq u ar ters) altera uk limited holmers farm way high wycombe buckinghamshire hp12 4xf united kingdom tel: (44) 1 494 602 000 fax: (44) 1 494 602 001 northern europe altera uk limited holmers farm way high wycombe buckinghamshire hp12 4xf united kingdom tel: (44) 1 494 602 020 fax: (44) 1 494 602 021 belgium alter a belgium katwilgw eg 7b 2050 antw er pen belgium tel: (32) 3 254 0420| f ax: (32) 3 254 0320 france altera france s.a.r.l. le mermoz 13 avenue morane saulnier 78140 velizy france tel: (33) 1 34 63 07 50 fax: (33) 1 34 63 07 51 germany altera gmbh max-planck-str. 5 d-85716 unterschleissheim germany tel: (49) 89 3218 250 fax: (49) 89 3218 2579 hong k ong altera hong kong suite 1008, tower 1 china hong kong city 33 canton road, tsimshatsui kowloon, hong kong tel: (852) 2377-0218 fax: (852) 2377-2811 it al y altera italia s.r.l. corso lombardia 75 autoporto pescarito 10099 san mauro, torinese (torino) italy tel: (39) 11 223 8588 fax: (39) 11 223 8589 j ap an altera japan, ltd. shinjuku mitsui building 2-1-1, nishi-shinjuku shinjuku-ku, tokyo 162-04 japan tel: (81) 3 3340 9480 fax: (81) 3 3340 9487 k orea altera korea youndang building, suite 501 144-23 samsung-dong, kangnam-ku seoul, k orea 135-090 tel: (82) 2 538-6895 f ax: (82) 2 538-6896 sweden altera ab sjoangsvagen 15 192 72 sollentuna sweden tel: (46) 8 626 60 91 fax: (46) 8 626 60 99 altera regional offices (continued) oregon altera corporation 11000 s.w. stratus street, suite 330-17 beaverton, or 97008 tel: (503) 643-8447 fax: (503) 644-2345 t e xas altera corporation 5080 spectrum drive, suite 812w dallas, tx 75248 tel: (972) 701-2330 fax: (972) 701-2331 texas (contin ued) altera corporation 9430 research boulevard echelon iv, suite 400 austin, tx 78759 tel: (512) 343-4542 fax: (512) 418-1186 canada altera corporation 300 march road, suite 601b kanata, ontario k2k 2e2 canada tel: (613) 599-3141 fax: (613) 599-3143
lpm quick reference guide december 1996 a-cat-lpm-01 altera, max, max+plus, max+plus ii, and flex are trademarks and/or service marks of altera corporation in the united states and other countries. altera corporation acknowledges the trademarks of other organizations for their respective products or services ment ioned in this document, specifically: verilog and cadence are a registered trademark of cadence design systems, inc. data i/o is a registered trademark of data i/o corporation. exemplar logic is a registered trademark of exemplar logic, inc. mentor graphics is a registered trademark of mentor graphics corporation. minc is a registered trademark of minc incorporated. sparcstation is a trademark of sparc international, inc. and is licensed exclusively to sun microsystems, inc. sun workstation is a registered trademark, and sun is a trademark of sun microsystems, in c. synopsys is a registered trademark of synopsys, inc. veribest is a registered trademark of veribest inc. viewlogic is a registered trademark ot viewlogic systems, inc. altera reserves the right to make changes, without notice, in the devices or the device specifications identified in this docum ent. altera advises its customers to obtain the latest version of device specifications to verify, before placing orders, that the information being re lied upon by the customer is current. altera warrants performance of its semiconductor products to current specifications in accordance with altera?s sta ndard warranty. testing and other quality control techniques are used to the extent altera deems such testing necessary to support this warranty. unles s mandated by government requirements, specific testing of all parameters of each device is not necessarily performed. in the absence of writ ten agreement to the contrary, altera assumes no liability for altera applications assistance, customer?s product design, or infringement of patents or copyrights of third parties by or arising from use of semiconductor devices described herein. nor does altera warrant or represent any patent right , copyright, or other intellectual property right of altera covering or relating to any combination, machine, or process in which such semiconductor devices might be or are used. altera?s products are not authorized for use as critical components in life support devices or systems without the express writ ten approval of the president of altera corporation. as used herein: 1. life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) suppo rt or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expe cted to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. products mentioned in this document are covered by one or more of the following u.s. patents: 5,574,893; 5,572,717; 5,572,148; 5,572,067; 5,570,040; 5,567,177; 5,563,592; 5,557,217; 5,555,214; 5,550,842; 5,550,782; 5,548,552; 5,548,228; 5,543,732; 5,543,730; 5,541,530; 5,537, 295; 5,537,057; 5,525,917; 5,523.247; 5,517,186; 5,498,975; 5,495,182; 5,493,519; 5,477,474; 5,463,328; 5,444,394; 5,438,295; 5,436,575; 5,436,574; 5,434, 514; 5,432,467; 5,414,312; 5,399,922; 5,384,499; 5,376,844; 5,375,086; 5,371,422; 5,369,314; 5,359,243; 5,359,242; 5,353,248; 5,352,940; 5,350,954; 5,349, 255; 5,341,308; 5,341,048; 5,341,044; 5,329,487; 5,317,212; 5,317,210; 5,315,172; 5,309,046; 5,301,416; 5,294,975; 5,285,153; 5,280, 203; 5,274,581; 5,272,368; 5,268,598; 5,260,611; 5,260,610; 5,258,668; 5,247,478; 5,247,477; 5,243,233; 5,241,224; 5,237,219; 5,220, 533; 5,220,214; 5,200,920; 5,187,392; 5,166,604; 5,162,680; 5,144,167; 5,138,576; 5,128,565; 5,121,006; 5,111,423; 5,097,208; 5,091, 661; 5,066,873; 5,045,772; 4,969,121; 4,930,107; 4,930,098; 4,930,097; 4,912,342; 4,903,223; 4,899,070; 4,899,067; 4,871,930; 4,864, 161; 4,831,573; 4,785,423; 4,774,421; 4,713,792; 4,677,318; 4,617,479; 4,609,986; 4,020,469; and certain foreign patents. copyright ? 1996 altera corporation. all rights reserved. printed on recycled paper.

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